The present invention is generally related to a parallelable power supply, and more particularly the present invention is directed to an isolation device for a parallelable power supply, which is agreeable to isolate the parallelable power supply from a reverse current when a reverse current is induced at the voltage output terminal of the parallelable power supply.
For the purpose of increasing the output power and promoting the reliability for a power supply system, it is desirable to connect two or more parallelable power supplies in parallel to provide a combined output power supply to a load. As shown in FIG. 1, the parallelized power supply system consists of two parallelable power supplies 11 and 12, each of which is connected in parallel by a voltage bus 13 and provides a combined power output to a load 16. The advantage of the parallelized power supply system of FIG. 1 is that in case one parallelable power supply is failed to supply power, the other one can continuously supply power without affecting the operation of the other electronic circuits in the parallelized power supply system.
However, when two or more parallelable power supplies are connected in parallel to supply combined power, and if one parallelable power supply provides an output voltage with a voltage level lower than the voltage level for which the other parallelable power supplies can provide, or one parallelable power supply is failed, an unwanted reverse current will be induced to flow into the defective parallelable power supply, so that the defective parallelable power supply behaves as a load for other parallelable power supplies. Regarding the defective parallelable power supply, its output becomes a load, which will cause a grave damage to the whole parallelized power supply system.
For the sake of averting the reverse current from flowing into the defective parallelable power supply, an isolation device is required to connect between the voltage output terminal of the parallelable power supply and the voltage bus 13 for isolating the parallelable power supply from the unwanted reverse current. In FIG. 1, two diodes 14 and 15 which are respectively placed between the voltage output terminal (not shown) of the parallelable power supplies 11 and 12 and the voltage bus 13 are taken as isolation devices for the parallelable power supplies 11 and 12. As well known in the art, the diode is substantially a unidirectional rectifying circuit. When a forward-biased voltage is applied to the diode, the diode will turn on and a forward current will be induced to flow from the anode to the cathode of the diode; on the contrary, when a reverse-biased voltage is applied to the diode, the diode will turn off instantaneously. Considering the particular electric features of the diode, it is found that the diode is quite suitable to be applied for isolating the reverse current from the parallelable power supply.
Unfortunately, the prior art of placing diode in the parallelized power supply system to prevent the reverse current will inevitably bring about some unconquerable problems. The major problem encountered by the prior art is that when the current flows through the P-N junction of the diode, a considerable power loss will be produced. In view of the foregoing problems, taking a transistor such as a field effect transistor (FET) to replace the diodes as the isolation device to prevent the reverse current for the parallelable power supply will reduce the power loss in the parallelized power supply system and enhance the overall efficiency of the parallelized power supply system.
Nonetheless, the known FET is a bi-directional circuit, and the fundamentals for turning on and off the FET is not as simple as the diode. Therefore, if it is intended to use the FET as the isolation device for preventing the reverse current from flowing into the parallelable power supply, a high speed and high accuracy control circuit must be provided to control the FET to turn on when a forward current flows out of the parallelable power supply and control the FET to turn off when a reverse current flows into the parallelable power supply.
It is highly desirable to provide an isolation device which can rapidly and precisely prevent the reverse current from flowing into the parallelable power supply, while can address the problem of significant power loss encountered by the prior art of using diode as an isolation device for the parallelable power supply.
It is therefore an object of the present invention to provide an isolation device adapted for a parallelable power supply which can rapidly and precisely prevent a reverse current from flowing into the parallelable power supply under the circumstances of low power loss.
It is a further object of the present invention to provide an isolation device for use in a parallelized power supply system for preventing a reverse current from flowing into one of the parallelable power supplies, in which the parallelized power supply system is constructed from a plurality of parallelable power supplies connected in parallel by a voltage bus.
According to a first preferred embodiment of the present invention, an isolation device for protecting the parallelable power supply from a reverse current flowing from a load to the parallelable power supply includes a transistor having a first terminal connected to an output voltage terminal of the parallelable power supply and a second terminal connected to the load, and a transistor control circuit for driving the transistor to turn on when a forward current flows from the parallelable power supply into the load and driving the transistor to turn off when a reverse current flows from the load into the parallelable power supply.
The transistor is preferably embodied in a field effect transistor (FET), and the aforementioned transistor control circuit further comprises a voltage comparator circuit including a comparator for comparing an output voltage of the parallelable power supply with an external voltage of the parallelable power supply and in response thereto, outputs a first control signal; a duty comparator circuit including a comparator for comparing a voltage representing an output duty of the transformer of the parallelable power supply with a reference voltage and in response thereto, outputs a second control signal; and a transistor driving circuit for performing a logic AND operation with the first control signal and the second control signal for driving the transistor to turn on or off in response to a result of the logic AND operation, so as to disallow a reverse current to flow into the parallelable power supply.
In addition, in the first preferred embodiment of the present invention, the transistor control circuit further comprises an auxiliary circuit for preventing a reverse current from flowing into the parallelable power supply when the parallelable power supply is short-circuited. The auxiliary circuit is constructed of a memory element, for example, a capacitor, which memorizes the output voltage level of the parallelable power supply and discharging the electric energy stored therein to an inverting input terminal of the comparator of the voltage comparator circuit when the parallelable power supply is short-circuited, and a voltage switch, for example, a diode, for being controlled by the memory element to establish a discharge loop for the memory element to discharge the electric energy stored therein to an inverting input terminal of the comparator of the voltage comparator circuit, thereby driving the comparator of the voltage comparator circuit to turn the transistor off.
An alternative circuit topology for the above-described auxiliary circuit is provided with a second embodiment of the present invention. The auxiliary circuit according to the second embodiment of the present invention is constructed of a memory element, for example, a capacitor, which memorizes the output voltage level of the parallelable power supply and discharging the electric energy stored therein when the parallelable power supply is short-circuited, and a gate driving circuit which is formed of a bipolar junction transistor (BJT) for driving the transistor to turn off when the parallelable power supply is short-circuited by way of receiving the discharged electric energy from the memory element.
In relation to a further aspect of the present invention, an isolation device for use in a parallelized power supply system, wherein the parallelized power supply system is formed of two or more parallelable power supplies connected in parallel by a voltage bus, is provided to couple in series between an voltage output terminal of one of the parallelable power supplies and the voltage bus for preventing a reverse current from flowing into the corresponding one of the parallelable power supplies. The isolation device comprises a field effect transistor (FET) having a first terminal connected to the voltage output terminal of the corresponding one of the parallelable power supply and the voltage bus, a voltage comparator circuit comprising a voltage comparator which compares an output voltage of the corresponding one of the parallelable power supplies with an input voltage of the voltage bus and in response thereto, outputs a first control signal, a duty comparator circuit comprising a comparator which compares a voltage representing an output duty of a transformer of the corresponding one of the parallelable power supplies with a reference voltage and in response thereto, outputs a second control signal, a transistor driving circuit which performs a logic AND operation with the first and the second control signals and drives the FET to turn on or off depending on a result of the logic AND operation, so as to prevent a reverse current from flowing into the corresponding one of the parallelable power supplies.
According to a second aspect of the present invention, the isolation device further comprises an auxiliary circuit for preventing a reverse current from flowing into the parallelable power supply when the parallelable power supply is short-circuited. The auxiliary circuit is constructed of a memory element, for example, a capacitor, which memorizes the output voltage level of the parallelable power supply and discharging the electric energy stored therein to an inverting input terminal of the comparator of the voltage comparator circuit when the parallelable power supply is short-circuited, and a voltage switch, for example, a diode, for being controlled by the memory element to establish a discharge loop for the memory element to discharge the electric energy stored therein to an inverting input terminal of the comparator of the voltage comparator circuit, so as to drive the comparator of the voltage comparator circuit to turn the FET off.
The foregoing auxiliary circuit can be designed to have a different layout. According to a second embodiment of the present invention, the auxiliary circuit is constructed of a memory element, for example, a capacitor, which memorizes the output voltage level of the parallelable power supply and discharges the electric energy stored therein when the parallelable power supply is short-circuited, and a gate driving circuit which is formed of a bipolar junction transistor (BJT) for driving the FET to turn off when the parallelable power supply is short-circuited by way of receiving the discharged electric energy from the memory element.
Now the foregoing and other features and advantages of the present invention will be more clearly understood through the following descriptions with reference to the accompanying drawings, in which: